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http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/1178| An area/performance trade-off analysis of a GF(2m) multiplier architecture for elliptic curve cryptography | |
| MIGUEL MORALES SANDOVAL CLAUDIA FEREGRINO URIBE RENE ARMANDO CUMPLIDO PARRA IGNACIO ALGREDO BADILLO | |
| Acceso Abierto | |
| Atribución-NoComercial-SinDerivadas | |
| A hardware architecture for GF(2m) multiplication and its evaluation in a hardware architecture for elliptic curve scalar multiplication is presented. The architecture is a parameterizable digit-serial implementation for any field order m. Area/performance trade-off results of the hardware implementation of the multiplier in an FPGA are presented and discussed. | |
| Elsevier Ltd | |
| 2009 | |
| Artículo | |
| Inglés | |
| Estudiantes Investigadores Público en general | |
| Morales-Sandoval, M., et al., (2009). An area/performance trade-off analysis of a GF(2m) multiplier architecture for elliptic curve cryptography, Computers and Electrical Engineering (35): 54–58 | |
| CIENCIA DE LOS ORDENADORES | |
| Versión publicada | |
| publishedVersion - Versión publicada | |
| Aparece en las colecciones: | Artículos de Ciencias Computacionales |
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| Fichero | Tamaño | Formato | |
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| 2009-FeregrinoUribeClaudia-An Area-Performance Trade-Off Analysis.pdf | 182.15 kB | Adobe PDF | Visualizar/Abrir |