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http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/2124| Study and comparison of CMOS layouts for applications in analog circuits | |
| MONICO LINARES ARANDA CARLOS ZUÑIGA ISLAS | |
| Acceso Abierto | |
| Atribución-NoComercial-SinDerivadas | |
| Integrated circuit (IC) Layout Operational amplifier Serpentine | |
| This study presents different layouts techniques (serpentine, concentric, interdigitated) applied to a differential amplifier designed in commercial technology CMOS (0.6 μm). It was observed that serpentine technique improves by 6 to 7 electrical parameters, where area was reduced (64%) and power consumption diminishes until a 57% with respect to conventional technique. Thus designer can optimally use different abstraction levels during integrated circuits (IC) design, by applying the best layout technique towards efficient systems. | |
| Journal of Scientific and Industrial Research | |
| 2012-04 | |
| Artículo | |
| Inglés | |
| Estudiantes Investigadores Público en general | |
| López, Francisco, et al., (2012), Study and comparison of CMOS layouts for applications in analog circuits, Journal of Scientific and Industrial Research, Vol. 71(4):257–261 | |
| ELECTRÓNICA | |
| Versión aceptada | |
| acceptedVersion - Versión aceptada | |
| Aparece en las colecciones: | Artículos de Electrónica |
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| 71 Zuñiga_2012_ScientificIndustrial71.pdf | 477.75 kB | Adobe PDF | Visualizar/Abrir |