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http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/1397| A versatile hardware architecture for a constant false alarm rate processor based on a linear insertion sorter | |
| JOSE ROBERTO PEREZ ANDRADE RENE ARMANDO CUMPLIDO PARRA CLAUDIA FEREGRINO URIBE FERNANDO MARTIN DEL CAMPO RAMIREZ | |
| Acceso Abierto | |
| Atribución-NoComercial-SinDerivadas | |
| CFAR processor Software defined radar Hardware architecture | |
| Constant False Alarm Rate (CFAR) algorithms are used in digital signal processing applications to extract targets from background in noisy environments. Some examples of applications are target detection in radar environments, image processing, medical engineering, power quality analysis, features detection in satellite images, Pseudo-Noise (PN) code detectors, among others. This paper presents a versatile hardware architecture that implements six variants of the CFAR algorithm based on linear and nonlinear operations for radar applications. Since some implemented CFAR algorithms require sorting the input samples, a linear sorter based on a First In First Out (FIFO) schema is used. The proposed architecture, known as CFAR processor, can be used as a specialized module or co-processor for Software Defined Radar (SDR) applications. The results of implementing the CFAR processor on a Field Programmable Gate Array (FPGA) are presented and discussed. | |
| Elsevier Inc. | |
| 2010 | |
| Artículo | |
| Inglés | |
| Estudiantes Investigadores Público en general | |
| Perez-Andrade, R., et al., (2010). A versatile hardware architecture for a constant false alarm rate processor based on a linear insertion sorter, Digital Signal Processing, (20): 1733–1747 | |
| CIENCIA DE LOS ORDENADORES | |
| Versión aceptada | |
| acceptedVersion - Versión aceptada | |
| Aparece en las colecciones: | Artículos de Ciencias Computacionales |
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