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http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/165| Reliability enhancement of nanometer-scale digital circuits | |
| HECTOR LUIS VILLACORTA MINAYA | |
| VICTOR HUGO CHAMPAC VILELA Jaume Segura Garcia | |
| Acceso Abierto | |
| Atribución-NoComercial-SinDerivadas | |
| Integrated circuits Nanotechnology Testing Reliability SRAM | |
| The aggressive scaling of CMOS process technology poses serious challenges on the lifetime reliability of ICs due to the stringent operating conditions and the increase of process parameter variations. Reliability has become an important concern of semiconductor industry and should be improved with each scaled technological node in order to enhance yield. From semiconductor perspective, reliability is the ability of a device to perform its required function under stated conditions for a specified period of time. A semiconductor device fails when the response parameters from the device can no longer perform its intended function. Device failure may occur at any moment of device's lifetime. As technology scales down, the likelihood of manufacturing defects such as open and bridge defects increases due to the growth rate of interconnections. Some of these defects are hard to be detected by traditional test methods and could result in test escapes posing reliability issues. In addition, soft errors have emerged as an important reliability concerns in SRAM memories due to lower node capacitance and more stringent operating conditions. | |
| Instituto Nacional de Astrofísica, Óptica y Electrónica | |
| 2014-05 | |
| Tesis de doctorado | |
| Inglés | |
| Estudiantes Investigadores Público en general | |
| Villacorta-Minaya H.L. | |
| ELECTRÓNICA | |
| Versión aceptada | |
| acceptedVersion - Versión aceptada | |
| Aparece en las colecciones: | Doctorado en Electrónica |
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| VillacortaMiHL.pdf | 16.82 MB | Adobe PDF | Visualizar/Abrir |