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Hardware–software platform for computing irreducible testors
Alejandro Rojas Hernández
RENE ARMANDO CUMPLIDO PARRA
Jesús Ariel Carrasco Ochoa
CLAUDIA FEREGRINO URIBE
José Francisco Martínez Trinidad
Acceso Abierto
Atribución-NoComercial-SinDerivadas
Feature selection
Testor theory
Custom architectures
FPGAs
In pattern recognition, feature selection is a very important task for supervised classification. The problem consists in, given a dataset where each object is described by a set of features, finding a subset of the original features such that a classifier that runs on data containing only these features would reach high classification accuracy. A useful way to find this subset of the original features is through testor theory. A testor is defined as a subset of the original features that allows differentiating objects from different classes. Testors are very useful particularly when object descriptions contain both numeric and non-numeric features. Computing testors for feature selection is a very complex problem due to exponential complexity, with respect to the number of features, of algorithms based on testor theory. Hardware implementation of testor computing algorithms helps to improve their performance taking advantage of parallel processing for verifying if a feature subset is a testor in a single clock cycle. This paper introduces an efficient hardware–software platform for computing irreducible testors for feature selection in pattern recognition. Results of implementing the proposed platform using a FPGA-based prototyping board are presented and discussed.
Elsevier Ltd
2012
Artículo
Inglés
Estudiantes
Investigadores
Público en general
Rojas-Hernández, A., et al., (2012). Hardware–software platform for computing irreducible testors, Expert Systems with Applications, (39): 2203–2210
CIENCIA DE LOS ORDENADORES
Versión aceptada
acceptedVersion - Versión aceptada
Aparece en las colecciones: Artículos de Ciencias Computacionales

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