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http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/2276| On an external memory scheme for processor arrays | |
| JOSE ROBERTO PEREZ ANDRADE CESAR TORRES HUITZIL RENE ARMANDO CUMPLIDO PARRA | |
| Acceso Abierto | |
| Atribución-NoComercial-SinDerivadas | |
| Prosessor arrays Loop-based Algorithms External Memory Interface FPGA | |
| The problem of generating memory interfaces between loop-based accelerators and external memory is gaining the attention from the high-level synthesis research community. This paper presents an external memory system for inserting/extracting data to/from a loop-based accelerator derived by a high-level synthesis approach. The memory system is composed by four architectural cases which could occur during hardware synthesis. The memory system is based on a global asynchronous local synchronous approach and the use of dualport memory banks. FPGA-based implementation results show that the proposed memory system is technologically achievable and provides a high-bandwidth without introducing communication overhead. | |
| Electronics Express | |
| 2013 | |
| Artículo | |
| Inglés | |
| Estudiantes Investigadores Público en general | |
| Perez-Andrade, R., et al., (2013). On an external memory scheme for processor arrays, Vol. 10 (14): 1-12 | |
| CIENCIA DE LOS ORDENADORES | |
| Versión aceptada | |
| acceptedVersion - Versión aceptada | |
| Aparece en las colecciones: | Artículos de Ciencias Computacionales |
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