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http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/2346| Area/performance trade-off analysis of an FPGA digit-serial GF(2m) Montgomery multiplier based on LFSR | |
| Ignacio Algredo Badillo CLAUDIA FEREGRINO URIBE Paris Kitsos RENE ARMANDO CUMPLIDO PARRA | |
| Acceso Abierto | |
| Atribución-NoComercial-SinDerivadas | |
| Montgomery Multiplication is a common and important algorithm for improving the efficiency of public key cryptographic algorithms, like RSA and Elliptic Curve Cryptography (ECC). A natural choice for implementing this time consuming multiplication defined on finite fields, mainly over GF(2m), is the use of Field Programmable Gate Arrays (FPGAs) for being reconfigurable, flexible and physically secure devices. FPGAs allow the implementation of this kind of algorithms in a broad range of applications with different area–performance requirements. In this paper, we explore alternative architectures for con- structing GF(2m) digit-serial Montgomery multipliers on FPGAs based on Linear Feedback Shift Registers (LFSRs) and study their area–performance trade-offs. Different Montgomery multipliers were implemented using several digits and finite fields to compare their perfor- mance metrics such as area, memory, latency, clocking frequency and throughput to show suitable configurations for ECC implementations using NIST recommended parameters. The results achieved show a notable improvement against FPGA Montgomery multiplier previ- ously reported, achieving the highest throughput and the best efficiency. | |
| Elsevier Ltd | |
| 2013 | |
| Artículo | |
| Inglés | |
| Estudiantes Investigadores Público en general | |
| Morales, M., et al., (2013). Area/performance trade-off analysis of an FPGA digit-serial GF(2m)Montgomery multiplier based on LFSR, Computers and Electrical Engineering, Vol. (39): 542–549 | |
| CIENCIA DE LOS ORDENADORES | |
| Versión aceptada | |
| acceptedVersion - Versión aceptada | |
| Aparece en las colecciones: | Artículos de Ciencias Computacionales |
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