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http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/268| A CMOS automatic gain control design based on piece-wise linear circuits | |
| DAVID MORO FRIAS | |
| MARIA TERESA SANZ PASCUAL | |
| Acceso Abierto | |
| Atribución-NoComercial-SinDerivadas | |
| Automatic gain control Piece-wise linear Winner-take-all | |
| In many electronic systems, a circuit capable of reducing the dynamic range of a signal is needed. An Automatic Gain Control (AGC) system is a complex circuit that maintains its output signal amplitude relatively constant, independently of the input variations. The time response of the AGC must also be constant, in order to maximize the system bandwidth and to reduce acquisition times. In this thesis a novel method to design and implement an AGC loop is presented, based on piece-wise linear (PWL) circuits. This PWL technique is used to design an exponential and logarithmic pre-distortion circuits which are implemented inside the AGC loop in order to have a linear-in-dB system and, as a consequence, to obtain a constant settling time AGC response. Also, two exponential variable gain amplifiers (VGA) and a peak detector were designed using the PWL predistortion circuits mentioned before. Thus, a complete AGC loop is implemented and tested at the laboratory to probe the validity of the proposed blocks. In Chapter 1 a brief introduction is presented, describing the principal AGC blocks, its basic operation, types of AGCs and finally AGC applications are mentioned. In Chapter 2 a PWL exponential pre-distortion circuit was proposed, based on current mirrors and a Winner-Take-All circuit. This approach is technology-independent, as it does not rely on the quadratic behavior of MOS transistors in strong inversion, and remains therefore valid for deep submicron CMOS processes, as opposed to former exponential approximations found in literature. Moreover, the proposed exponential pre-distortion circuit is not limited to a certain range of validity. In other words, the range of validity can be extended by adding segments to the implementation, at a cost of area and power consumption. The proposed approach was validated with experimental results from a 6-segment prototype, which showed a very wide linear-in-dB range of 41.97dB with 2.55dB maximum error. | |
| Instituto Nacional de Astrofísica, Óptica y Electrónica | |
| 2013-06 | |
| Tesis de doctorado | |
| Inglés | |
| Estudiantes Investigadores Público en general | |
| Moro-Frias D. | |
| ELECTRÓNICA | |
| Versión aceptada | |
| acceptedVersion - Versión aceptada | |
| Aparece en las colecciones: | Doctorado en Electrónica |
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| Fichero | Descripción | Tamaño | Formato | |
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| MoroFrD.pdf | 11.78 MB | Adobe PDF | Visualizar/Abrir |