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http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/692| Electrical modeling and optimization of multilayer via transitions for fully-integrated systems | |
| GAUDENCIO HERNANDEZ SOSA | |
| REYDEZEL TORRES TORRES | |
| Acceso Abierto | |
| Atribución-NoComercial-SinDerivadas | |
| High-speed techniques Integrated circuit packaging Modeling | |
| Due to the advances in electronics technology, today’s modern life is inevitably dependent on the complex convergence of diverse technologies into products designed to provide solutions in many applications (e.g., computing, communication, biomedical, etc.). In this way, the concept of fully-integrated “convergent electronic systems” has emerged. As promissory approach for implementing reliable fully-integrated systems, System-On-Package (SOP) technology proposes the integration of active and passive components into a single package. Nonetheless, SOP presents important challenges over traditional packaging due to the presence of multiple ICs, embedded passives and other components connected within the package. On the other hand, high-density substrates with narrow traces widths and thousands of vias in order to achieve vertical integration of different ICs working at higher speed is a key enabler technology for SOP. Unfortunately, electrical discontinuities introduced by via transitions are the main limiting factors for the ultimate performance of SOP interconnects. As a result, the development of interconnects capable of guiding broadband digital signals without degrading the signal integrity plays a key role in the SOP implementation. Thus, due to the importance of vias for fully-integrated systems based on SOP, fast and accurate techniques to model vias in multilayered high-density packages are developed in this thesis. Furthermore, techniques to mitigate the signal integrity problems related to vias are proposed. Among the contributions that the reader will find in this document are novel full-wave/circuit modeling methodologies for vias in high-density packages, return loss and crosstalk mitigation techniques which allow extending the useful bandwidth of chip-to-chip links. Rigorous theoretical analyses were carried out accompanied by exhaustive simulations in the time and frequency domains to develop and demonstrate the models and methodologies proposed in this thesis. Moreover, several prototypes were designed and fabricated as part of this project to serve as test vehicles that allow the verification of the mitigation techniques in an advanced SOP technology. | |
| Instituto Nacional de Astrofísica, Óptica y Electrónica | |
| 2011-11 | |
| Tesis de doctorado | |
| Inglés | |
| Estudiantes Investigadores Público en general | |
| Hernandez-Sosa G. | |
| ELECTRÓNICA | |
| Versión aceptada | |
| acceptedVersion - Versión aceptada | |
| Aparece en las colecciones: | Doctorado en Electrónica |
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| Fichero | Tamaño | Formato | |
|---|---|---|---|
| HernandezSoG.pdf | 5.89 MB | Adobe PDF | Visualizar/Abrir |