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http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/845| Reliability analysis and improvement of nanoscale CMOS digital circuits | |
| ANDRES FELIPE GOMEZ CHACON | |
| VICTOR HUGO CHAMPAC VILELA | |
| Acceso Abierto | |
| Atribución-NoComercial-SinDerivadas | |
| Circuit Reliability NBTI PBTI Aging monitoring Gate sizing Critical paths Process variations | |
| Reliability degradation due to transistor aging is a major challenge in the design of digital integrated circuits for current and future technology nodes. Bias Temperature Instability (BTI) is the dominant aging mechanisms in digital circuits. BTI gradually increases the device's threshold voltage (Vth) over the lifetime, which in turn degrades circuit speed, and ultimately, it may cause a faulty operation. Circuit performance degradation due to BTI is highly dependent on the operating conditions such as the executed workloads by the circuit and the operating temperature. Moreover, variability in devices parameter due to process variations aggravate the reliability issues. These effects need to be properly accounted during circuit design phase to obtain electronic products with improved lifetime. Conventional worst-case one-time guardbans to deal with aging due to BTI are becoming too large with technology scaling, which leads to conservative designs with reduced performance. This thesis addresses BTI aging issues from two different perspectives: Aging Monitoring: Aging sensors are introduced in the circuit critical paths (CP) in order to detect when they are close to violate timing speci_cations due to BTI. Then, failure-prevention actions (i.e. increase system clock period) can take place. This thesis proposes a methodology to efficiently identify, at an early design phase, the critical paths of the circuit that should be monitored for reliable on-line aging tracking. The major challenges addressed for critical path selection are the uncertainty caused by process parameters variations, the uncertainty on spatial correlation between gates since gate placement in the layout is unknown at early design phase, and the uncertainty of the operating workload of the circuit, which is unknown in advance at the design phase. Reliable Circuit Design: Among the gates that belong to the critical paths of a circuit, some of them are more efcient to be re-sized to compensate aging degradation. This thesis proposes a circuit design methodology to reduce the guardband required for a circuit by smart selection an sizing of the circuit's critical gates. Gate selection metrics are proposed to guide the sizing process of the circuits. One of the most important parameters taken into account by the metrics is the statistical path delay sensitivity to gate sizing, which depends on process variations, spatial correlation between gates, and the BTI degradation of the devices | |
| Instituto Nacional de Astrofísica, Óptica y Electrónica | |
| 06-12-2017 | |
| Tesis de doctorado | |
| Inglés | |
| Estudiantes Investigadores Público en general | |
| Gómez-Chacón AF | |
| CIRCUITOS INTEGRADOS | |
| Versión aceptada | |
| acceptedVersion - Versión aceptada | |
| Aparece en las colecciones: | Doctorado en Electrónica |
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| Fichero | Tamaño | Formato | |
|---|---|---|---|
| GomezChAF.pdf | 9.76 MB | Adobe PDF | Visualizar/Abrir |