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http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/996| Design and Implementation of a Non-pipelined MD5 Hardware Architectures using a new functional description | |
| IGNACIO ALGREDO BADILLO CLAUDIA FEREGRINO URIBE RENE ARMANDO CUMPLIDO PARRA MIGUEL MORALES SANDOVAL | |
| Acceso Abierto | |
| Atribución-NoComercial-SinDerivadas | |
| MD5 algorithm Hardware design FPGA implementation Hardware architectures | |
| MD5 is a cryptographic algorithm used for authentication. When implemented in hardware, the performance is affected by the data dependency of the iterative compression function. In this paper, a new functional description is proposed with the aim of achieving higher throughput by mean of reducing the critical path and latency. This description can be used in similar structures of other hash algorithms, such as SHA-1, SHA-2 and RIPEMD-160, which have comparable data dependence. The proposed MD5 hardware architecture achieves a high throughput/area ratio, results of implementation in an FPGA are presented and discussed, as well as comparisons against related works. | |
| IEICE Transactions on Information and Systems | |
| 2008-10 | |
| Artículo | |
| Inglés | |
| Estudiantes Investigadores Público en general | |
| Alegro-Badillo, I., et al., (2008). Design and Implementation of a Non-pipelined MD5 Hardware Architectures using a new functional description, Vol. E91-D (10): 2519-2523 | |
| CIENCIA DE LOS ORDENADORES | |
| Versión aceptada | |
| acceptedVersion - Versión aceptada | |
| Aparece en las colecciones: | Artículos de Ciencias Computacionales |
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| Fichero | Tamaño | Formato | |
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| 2008-FeregrinoUribeClaudia-Design and Implementation.pdf | 965.74 kB | Adobe PDF | Visualizar/Abrir |