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http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/1229| On the characterization of the trapped charge in FG-CMOS inverters | |
| JESUS EZEQUIEL MOLINAR SOLIS RODOLFO ZOLA GARCIA LOZANO IVAN RODRIGO PADILLA CANTOYA ALEJANDRO DIAZ SANCHEZ JOSE MIGUEL ROCHA PEREZ | |
| Acceso Abierto | |
| Atribución-NoComercial-SinDerivadas | |
| Neuron-MOS vMOS Floating-gate transistors | |
| In this work, an experimental comparison between measured FG CMOS inverters using the quasifloating gate (QFG) and layout-based (L-b) techniques for charge removal in the Floating-gate (FG) and simulations through PSpice is presented. The experiment was developed through the measurements of 40 different IC’s with a total of 200 FG and QFG CMOS inverters characterized on AMI C5FN 0.5 lm technology. The data obtained shows that the layout-based technique reduces the initial charge present at the FG, but presents a very small residual charge. Nevertheless, the offset associated to the charge follows a normal distribution and is predictable. Comparison between measured QFG inverters and simulations shows that the high resistance parasitic diode must be modeled accurately for a proper simulation. | |
| Springer Science+Business Media | |
| 2009 | |
| Artículo | |
| Inglés | |
| Estudiantes Investigadores Público en general | |
| Molinar-Solis, J.E., et al., (2009). On the characterization of the trapped charge in FG-CMOS inverters, Analog Integr Circ Sig Process (61): 191–198 | |
| ELECTRÓNICA | |
| Versión aceptada | |
| acceptedVersion - Versión aceptada | |
| Aparece en las colecciones: | Artículos de Electrónica |
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