Please use this identifier to cite or link to this item: http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/1595
On the implementation of a hardware architecture for an audio data hiding system
JOSE JUAN GARCIA HERNANDEZ
CLAUDIA FEREGRINO URIBE
RENE ARMANDO CUMPLIDO PARRA
CAROLINA RETA CASTRO
Acceso Abierto
Atribución-NoComercial-SinDerivadas
Data hiding
Audio signal
FPGA
Multi-channel processing
Data hiding systems have emerged as a solution against the piracy problem, particularly those based on quantization have been widely used for its simplicity and high performance. Several data hiding applications, such as broadcasting monitoring and live performance watermarking, require a real-time multi-channel behavior. While Digital Signal Processors (DSP) have been used for implementing these schemes achieving real-time performance for audio signal processing, custom hardware architectures offer the possibility of fully exploiting the inherent parallelism of this type of algorithms for more demanding applications. This paper presents an efficient hardware implementation of a Rational Dither Modulation (RDM) algorithm-based data hiding system in the Modulated Complex Lapped Transform (MCLT) domain. In general terms, the proposed hardware architecture is conformed by an MCLT processor, an Inverse MCLT processor, a Coordinate Rotation Digital Computer (CORDIC) and an RDM-QIM processor. Results of implementing the proposed hardware architecture a Field Programmable Gate Array (FPGA) are presented and discussed.
Springer Science+Business Media
2011
Artículo
Inglés
Estudiantes
Investigadores
Público en general
Garcia-Hernandez, J.J., et al., (2011). On the implementation of a hardware architecture for an audio data hiding system, Journal of Signal Processing Systems (64): 457–468
CIENCIA DE LOS ORDENADORES
Versión aceptada
acceptedVersion - Versión aceptada
Appears in Collections:Reportes Técnicos de Ciencias Computacionales

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