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http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/1740| CMOS full-adders for energy-efficient arithmetic applications | |
| MARIANO AGUIRRE HERNANDEZ MONICO LINARES ARANDA | |
| Acceso Abierto | |
| Atribución-NoComercial-SinDerivadas | |
| Arithmetic Full-adder High-speed Low-power | |
| We present two high-speed and low-power full-adder cells designed with an alternative internal logic structure and pass-transistor logic styles that lead to have a reduced power-delay product (PDP). We carried out a comparison against other full-adders reported as having a low PDP, in terms of speed, power consumption and area. All the full-adders were designed with a 0.18-μm CMOS technology, and were tested using a comprehensive testbench that allowed to measure the current taken from the full-adder inputs, besides the current provided from the power-supply. Post-layout simulations show that the proposed full-adders outperform its counterparts exhibiting an average PDP advantage of 80%, with only 40% of relative area. | |
| IEEE | |
| 2011 | |
| Artículo | |
| Inglés | |
| Estudiantes Investigadores Público en general | |
| Aguirre-Hernandez, M. & Linares-Aranda, M. (2011). CMOS full-adders for energy-efficient arithmetic applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 19, (4): 718-721 | |
| ELECTRÓNICA | |
| Versión aceptada | |
| acceptedVersion - Versión aceptada | |
| Aparece en las colecciones: | Artículos de Electrónica |
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| 26 Aguirre_2011_IEEE19.pdf | 1.09 MB | Adobe PDF | Visualizar/Abrir |