Por favor, use este identificador para citar o enlazar este ítem:
http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/1779| Impedance matching of traces and multilayer via transitions for on-package links | |
| Gaudencio Hernández Sosa Reydezel Torres Torres | |
| Acceso Abierto | |
| Atribución-NoComercial-SinDerivadas | |
| Impedance matching Return loss Vias | |
| A method for achieving impedance matching between traces and multilayer via transitions in on-package chip-to-chip links is presented. The method allows determining of the geometry for minimizing the return loss when a signal propagates through the link. For this purpose, analytical equations are derived using a physically-based equivalent circuit to represent the input impedance of multilayer via transitions. S -parameter measurements performed to optimized links using the method demonstrate the usefulness of the proposal. | |
| IEEE | |
| 2011 | |
| Artículo | |
| Inglés | |
| Estudiantes Investigadores Público en general | |
| Hernandez-Sosa, G., et al., (2011). Impedance matching of traces and multilayer via transitions for on-package links, IEEE Microwave and Wireless Components Letters, Vol. 21, (11): 595-597 | |
| ELECTRÓNICA | |
| Versión aceptada | |
| acceptedVersion - Versión aceptada | |
| Aparece en las colecciones: | Artículos de Electrónica |
Cargar archivos:
| Fichero | Tamaño | Formato | |
|---|---|---|---|
| 40 Hernandez_2011_IEEE21-11.pdf | 431.8 kB | Adobe PDF | Visualizar/Abrir |