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http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/1899| A multi-cycle fixed point square root module for FPGAs | |
| Fernando Martín del Campo Ramírez ALICIA MORALES REYES JOSE ROBERTO PEREZ ANDRADE RENE ARMANDO CUMPLIDO PARRA ALDO GUSTAVO OROZCO LUGO CLAUDIA FEREGRINO URIBE | |
| Acceso Abierto | |
| Atribución-NoComercial-SinDerivadas | |
| Square root Non-restoring algorithm FPGA | |
| This paper presents a module that solves the square root by obtaining a number of more significant bits from a look-up table as an approximate root. A set of possible roots are then appended and squared for comparison to the original radicand, finely tuning the calculation. The module stops as soon as it finds an exact root, therefore not all entries take the same number of cycles, reducing the number of iterations required for full resolution. The proposed FPGA module overcomes a Xilinx’s logiCORE IP in terms of resources utilization and in several cases latency due to its flexible structure configuration. | |
| IEICE Electronics Express | |
| 2012 | |
| Artículo | |
| Inglés | |
| Estudiantes Investigadores Público en general | |
| Martin del Campo, F., et al., (2012). A multi-cycle fixed point square root module for FPGAs, IEICE Electronics Express, Vol. 9 (11): 971-977 | |
| CIENCIA DE LOS ORDENADORES | |
| Versión aceptada | |
| acceptedVersion - Versión aceptada | |
| Aparece en las colecciones: | Artículos de Ciencias Computacionales |
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