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http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/2343| FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256 | |
| Ignacio Algredo Badillo CLAUDIA FEREGRINO URIBE RENE ARMANDO CUMPLIDO PARRA MIGUEL MORALES SANDOVAL | |
| Acceso Abierto | |
| Atribución-NoComercial-SinDerivadas | |
| SHA-2 Hash function FPGA | |
| Hash function algorithms are widely used to provide security services of integrity and authentication, being SHA-2 the latest set of hash algorithms standardized by the US Federal Government. The main com- putation block in SHA-2 algorithms is governed by a loop with high data dependence for which several implementation strategies are explored in this work as well as designs efficiently mapped to hardware architectures. Four new different hardware architectures are proposed to improve the performance of SHA-256 algorithms, reducing the critical path by reordering some operations required at each iteration of the algorithm and computing some values in advance, as possible as data dependence allows. The pro- posed designs were implemented and validated in the FPGA Virtex-2 XC2VP-7. The achieved results show a significant improvement on the performance of the SHA-256 algorithm compared to similar previously proposed approaches, obtaining a throughput of 909 Mbps and an improved efficiency of 0.713 Mbps/ slice. | |
| Elsevier B.V. | |
| 2013 | |
| Artículo | |
| Inglés | |
| Estudiantes Investigadores Público en general | |
| Badillo, I.A., et al., (2013). FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256, Microprocessors and Microsystems, Vol. (37): 750–757 | |
| CIENCIA DE LOS ORDENADORES | |
| Versión aceptada | |
| acceptedVersion - Versión aceptada | |
| Aparece en las colecciones: | Artículos de Ciencias Computacionales |
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| 196. FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256.pdf | 1.03 MB | Adobe PDF | Visualizar/Abrir |