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http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/70| Study of the MOS transistor for applications in RF circuits | |
| FABIÁN ZÁRATE RINCÓN | |
| ROBERTO STACK MURPHY ARTEAGA REYDEZEL TORRES TORRES | |
| Acceso Abierto | |
| Atribución-NoComercial-SinDerivadas | |
| MOSFET Series parasitic resistances Hot carriers Equivalent circuit | |
| In recent years, there has been a growing interest in circuit design based on CMOS technology for higher frequency applications in academia and industry such as Taiwanese companies TSMC and UMC. For instance, this is the case in the design of low noise amplifiers (LNA) and voltage controlled oscillator (VCO). Moreover, the channel length is scaled down as it was initially predicted by Moore's Law, which results in an increasing of switching speed and transconductance. Currently, market leader companies in terms of circuit manufacturing such as TSMC and UMC are working in technology nodes from 40 nm to 250 nm and the implementation of 28 nm is in progress. Indeed, on-wafer MOSFET characterization at high frequency gives place to new extraction methods of equivalent circuit elements and suggestions for compact models such as BSIM, PSP and EKV. Even though the transistor is a four-terminal device, this is usually measured by means of a 2-port vector network analyzer because of the limitation in some laboratories and then, the source and substrate terminals are tied each other. As a consequence of this, the assessment of each parameter cannot be modeled as a function of the bulk-to-source voltage. In order to address this, a separate bulk terminal and a DC probe are used to properly take into account the effect of the substrate, which is not only useful for developing a correct extraction methodology but also for establishing a suitable hot-carrier stress condition. As a result of this, an accurate extraction methodology of the small-signal equivalent circuit elements under different bulk-to-source voltages is proposed, including the analysis of the MOSFET degradation induced by hot carrier injection. On the other hand, due to the geometry-dependent parasitics of the MOSFET, its corresponding variation with both intrinsic and extrinsic components is studied. For this purpose, a set of devices with different gate length and another one with different number of fingers were measured at high frequency. Then, a suitable scalable model that is in a good agreement with experimental data is provided. | |
| Instituto Nacional de Astrofísica, Óptica y Electrónica | |
| 2016-08 | |
| Tesis de doctorado | |
| Inglés | |
| Público en general | |
| Zarate-Rincon F. | |
| DISEÑO DE CIRCUITOS | |
| Aparece en las colecciones: | Doctorado en Electrónica |
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| Fichero | Descripción | Tamaño | Formato | |
|---|---|---|---|---|
| ZarateRiF.pdf | 2.61 MB | Adobe PDF | Visualizar/Abrir |