Please use this identifier to cite or link to this item: http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/1726
Noise margin and short-circuit current in FGMOS logics
Luis Fortino Cisneros Sinencio
ALEJANDRO DIAZ SANCHEZ
Jaime Ramírez Angulo
Acceso Abierto
Atribución-NoComercial-SinDerivadas
Floating-gate logic
Noise margin
FGMOS transistor
Even when floating-gate logics are very-low-voltage circuits, as power supply is reduced, large fan-in FGMOS gates are prone to fail. Thus, determining the negative impact of noise margin and short-circuit current in this type of circuits is crucial to achieve optimal operation for a particular application. For this reason, a systematic and reliable technique for obtaining the correlation between fan-in and supply voltage, simultaneously considering noise margin and short-circuit current, is proposed.
IEICE Electronics Express
2011
Artículo
Inglés
Estudiantes
Maestros
Público en general
Cisneros-Sinencio, L.F., et al., (2011). Noise margin and short-circuit current in FGMOS logics, IEICE Electronics Express, Vol. 8 (23): 1967-1971
ELECTRÓNICA
Versión aceptada
acceptedVersion - Versión aceptada
Appears in Collections:Artículos de Electrónica

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