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http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/2059| Testing of Stuck-Open Faults in Nanometer Technologies | |
| Víctor Hugo Champac Vilela JULIO CESAR VAZQUEZ HERNANDEZ | |
| Acceso Abierto | |
| Atribución-NoComercial-SinDerivadas | |
| Failure analysis Fault diagnosis Integrated circuit reliability | |
| Failure analysis and fault modeling of integrated circuits have always been fields that require continuous revision and update as manufacturing processes evolve. This paper discusses the new face of the well-known transistor stuck-open fault model in modern nanometer technologies and proposes new detection methods that improve the robustness of tests. VDimitris Gizopoulos, University of Athens | |
| IEEE Design & Test of Computers | |
| 2012-08 | |
| Artículo | |
| Inglés | |
| Estudiantes Investigadores Público en general | |
| Champac, V., et al., (2012), Testing of Stuck-Open Faults in Nanometer Technologies, IEEE Design & Test of Computers, Vol. 29(4): 80–91. | |
| ELECTRÓNICA | |
| Versión aceptada | |
| acceptedVersion - Versión aceptada | |
| Aparece en las colecciones: | Artículos de Electrónica |
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| Fichero | Tamaño | Formato | |
|---|---|---|---|
| 9 Champac_2012_IEEE29.pdf | 1 MB | Adobe PDF | Visualizar/Abrir |