Por favor, use este identificador para citar o enlazar este ítem:
http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/2060| Resistive bridge defect detection enhancement under parameter variations combining Low VDD and body bias in a delay based test | |
| Héctor Luis Villacorta Minaya Víctor Hugo Champac Vilela | |
| Acceso Abierto | |
| Atribución-NoComercial-SinDerivadas | |
| Resistive bridges Nanometer technologie CMOS technology | |
| Resistive bridges are a major class of defects in nanometer technologies that can escape test, posing a serious reliability risk for CMOS IC circuits. The increase of process parameter variations represents a challenge for resistive bridge detection using traditional test methods, and requires more efficient test methods to be developed. In this work, we show that resistive bridge detection improves by correlating the defect-induced extra circuit delay with the power supply voltage value and the reverse body bias (RBB) applied. A Timing Critical Resistance (Rᵗcrit) is defined as a metric to quantify the resistive bridge detection enhancement in the presence of process variations under a delay based test. We show that the smaller the supply voltage, the higher the resistive bridge detection which further enhances by applying RBB. Results are presented for a 65 nm CMOS technology. | |
| Microelectronics Reliability | |
| 2012-11 | |
| Artículo | |
| Inglés | |
| Estudiantes Investigadores Público en general | |
| Villacorta, H., et al., (2012), Resistive bridge defect detection enhancement under parameter variations combining Low VDD and body bias in a delay based test, Microelectronics Reliability, Vol. 52(11):2799–2804. | |
| ELECTRÓNICA | |
| Versión aceptada | |
| acceptedVersion - Versión aceptada | |
| Aparece en las colecciones: | Artículos de Electrónica |
Cargar archivos:
| Fichero | Tamaño | Formato | |
|---|---|---|---|
| 10 Champac_2012_Elsevier52.pdf | 857.83 kB | Adobe PDF | Visualizar/Abrir |