Please use this identifier to cite or link to this item: http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/2292
FGMOS flip-flop for low-power signal processing
Luis Fortino Cisneros Sinencio
ALEJANDRO DIAZ SANCHEZ
Acceso Abierto
Atribución-NoComercial-SinDerivadas
Digital integrated circuits
Low-power integrated circuits
FGMOS transistors
In this paper, a family of latches based on floating-gate MOS (FGMOS) transistors is presented. This family takes advantage on the fact that FGMOS logics process data using mostly passive devices, achieving small area and low-power, which is a requirement in modern electronics. Post-layout SPICE simulations using ON-Semiconductors 0.5μm CMOS process parameters show improvements over conventional CMOS logic families, making FGMOS latches ideal for low-power applications.
International Journal of Electronics
30-03-2013
Artículo
Inglés
Estudiantes
Investigadores
Público en general
Cisneros-Sinencio, Luis F., et al., (2013), FGMOS flip-flop for low-power signal processing, International Journal of Electronics, Vol. 100(12):1-9
ELECTRÓNICA
Versión aceptada
acceptedVersion - Versión aceptada
Appears in Collections:Artículos de Electrónica

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